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Design Verification Engineer Interview Questions
949 design verification engineer interview questions shared by candidates
Assertions,SV OOPS, Comp Arch
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
They asked detailed questions about memory and interconnect design in advanced systems. They also gave me a small assignment which I had to do online.
How we can integrate agents without them generating stimulus
UVM Concepts and Work Experience of previous project
do I know objective-oriented coding
Verification plan of any given design, assertions, what is coverage?
Given read and write freq, how to calculate FIFO depth?
Do you have prior experience with UVM and System Verilog
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