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Design Verification Engineer Interview Questions
949 design verification engineer interview questions shared by candidates
1.what are the problems you faced during your project?
OOP and polymorphism. Basic System Verilog and UVM coding.
Convert the RTL logic to a gatelvel netlist. Constraint question from system verilog.
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
Given an expression with brackets, Suggest a solution to check legality: Examples: ((), )(), (((} , {[()]
1. Basics of digital electronics like combinational gates, mux, flip flops, registers, finite state machines, Verliog/ RTL code. 2. Difference between i) setup and hold time, ii) synchronous and asynchronous rests(explain through verilog coding) , iii) mealy and moore iv) tasks and function v) combinational and sequential vi) blocking and non-blocking statements vii) inter and intra statement delay 3. Verilog code for flip flops and finite state machines. 4. Maximum operating frequency of the circuit which had a combo logic between 2 flip flops. (HINT: Setup and hold time equation's based ques) 5. Varying what factor in the equation of setup and hold time can the violation of setup and hold time can be eliminated. (HINT: By varying combo propagation time.) 6. Flip flop conversions, truth tables, a logic implementation through mux, kmaps. 7. ASIC flow diagram, what is netlist, what is RTL. 8. OOPS concepts, sorting algorithms, time complexity. 9. Types of interrupts, what happens when interrupt is called. 10. What is function, what is class. How a class is called. 11. Detecting a sequence through mealy and moore state machines.
1. constraints 2. assertions 3. UVM topology
7 questions total. One about arm products, 2 about coding in any programming language you want and 2 about coding in VHDL. Last question was if I Had any questions.
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