Mainly about the projects with respect to both theoretical and technical knowledge. Along with it, some SV and UVM related questions like constraints, coverages, semaphore etc
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Digital logic and C programming questions
They mostly concentrated on sv , uvm
Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult
Write the VHDL or Verilog code for a given state machine diagram.
A basic testplan scenario
what is the flow of UVM methodology, and structural view of verification ?
related to the offered role skills
basic SV questions
They asked me about functions and verilog.
Viewing 801 - 810 interview questions