Difference between TLM ports and Analysis ports
Design Verification Engineer Interview Questions
949 design verification engineer interview questions shared by candidates
Tell me something about yourself. Why you are choosing to be a VLSI Design or Verification Engineer. You are interested in data science and choosing VLSI, why?
Self introduction Skills Communication Projects Protocols
1.Digital. 2.verilog. 3.sv. 4.UVM. 5.tb development..
most of them r counters, propagation delay, assertion waveforms and codes, and discreptive.
Tell me about yourself
Difference between latch and ff, diff b/n system verilog and verilog, difference between blocking and non blocking,
How to iterate through a binary tree
Generate a 2Ghz clock and code the FSM (The one with the asynchronous reset) in verilog.
What did you do at your previous co-op employer?
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