1 is heavier than the other 5 marbles among 6 mables . given a weight to find the heavier one.
Design Verification Engineer Interview Questions
949 design verification engineer interview questions shared by candidates
The questions were : write a SV code to get unique random numbers, rand vs randc, write driver code etc.
2. Generate two arrays of length 10, whose elements are unique to each? Later he explained that all the 20 elements in both the arrays should be unique
1)Should be ready to write some logics (C/Verilog/System Verilog) on the spot . 2)Blocking and Non-Blocking. 3)Fork/join types and applications. 4)Test bench architecture blocks.(asked to write a generalized code to implement gen and bfm).
Rewrite UVM phasing.
An arbiter with an asynchronous reset receives four requests signals, R1, R2, R3, R4 and generates four grant signals, G1, G2, G3, G4. Request R1 has the highest priority and request R4 has the lowest priority. Draw the state diagram.
A base class has an init function and one child class also has an init function. What can you do if you want the child class to execute the base class' init function?
1) Implement Linked list in hardware 2) LIFO using queues only
What is Functional coverage and why it is needed
Verification of different designs. Some basic rtl design questions. Project related questions. UVM based questions
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