FSM: Pattern detection 101 in a given sequence --> Change design from Moore to Mealey machine; Lots of questions based on Computer Architecture ( Memory-Cache heirarchy), Test Case scenarios, Signal Tx-Rx rates based question,
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
f/3 counter design using FSM
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
A question about managing branching methodology when dealing with IP cores.
how to balance the pipeline stage to achieve any specific time period?
Implement Coverage for given scenario
How do u rate in RTRT and ADA
C++ related Questions
UVM , system verilog and scoreboars related questions.
Write SV assertion for a req/ack protocol
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