Design an FSM (explain Mealy and Moore machines/ differences between them)
Asic Design Engineer Interview Questions
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1. Swap function: difference between pass by value and pass by reference 2. Fibonacci series. Two implementation: for loop and recursive. 3. The usage of constant, constant functions 4. Detect sequence pattern in FSM.
Asked to design a FSM
All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc
what 's the steps of synthesis?
Questions on Flip-flops, tristate buffer, logic design
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
Design a two input XOR gate use 1 MUX.
Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.
Write UVM Monitor for the defined case.
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