How to debug a timing violation in the lab?
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
They asked me questions related to Static Timing Analysis. For example, things like calculating setup time and hold time slack for a path in a digital circuit.
Interview questions were on core electronics concepts. Digital electronics mainly
Basic Verilog code questions, such as latch inferences, correct assignations (not mixing blocking/non blocking), FSM, etc
CDC and related concepts. Clock main issues, metastability, glitching, etc, and the possible solutions
Where do you see yourself in 5 years?
Asked questions about clock domain crossing , low power techniques
What are setup time and hold time?
Static Timing Analysis questions.
Explain the last project
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