Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
basic concept of pipeline state machine of sequence detector C program of a function about pattern replace
STA algorithms.
Puzzles and a lot of RTL coding.
Design a Verilog module that generates the perfect squares of natural numbers starting from 4.
Explain ASIC Design Flow
Using 3 registers and two two-bit full adders, how to count to 9 given that one clock cycle is only enough the delay of a full adder.
Number of bits representation for a given math function
Write the equation for set-up time for the circuit described. Give the hold equation for the same
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