They checked your resume and asked the questions related to your classes.
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is a fpga and what is a lookup table?
What is your Ph.D. research?
Write a Fibonacci number generator in Verilog, output a number in each cycle.
Digital Design basics
Tell us about interesting problems you uncounted and how you solved them
Two questions： 1. 2 2bits comparators to 4 bits comparators, and reduce the delay to 1 units 1. data buffer like 0100000001, most simple rtl design to get the length (which is 9)
design sensor with minimal logic block
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