write a code to extract input and outputs
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
Cmos transistors use in makin various gates
To print out elements on 1/8th of the circumference of the circle
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
They checked your resume and asked the questions related to your classes.
Questions on the resume. SV constructs, FIFO depth, STA questions
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
The first interview asked basic technical questions about logic design, STA and FSM etc. The second one was RTL coding for synchronous FIFO with depth=5
Describe a time when you need to gather information from different sources to troubleshoot an issue.
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