Asked about Basic Signalling like Block Section Working, Logic Circuits, Control Table Checking, Signalling Plan, CBTC Principles, Automation in C#, Process Automation & outcome. Success Ratio & feasibility of Automation in Signalling
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
technical questions which are related to projects you have done
c++ basics - virtual functions, function vs task difference, coverage , constraints
write assertions for the given timing diagram
Tell me about yourself and your skills
Beschreiben Sie die OVM-Umgebung!
SV, UVM, Driver sequencer handshake mechanism
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
Verilog code for basic circuits
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
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