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Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Blocking vs non blocking in Verilog and Logic Design. Pipelining concept. Basic algorithms, time/space complexity. Virtual functions in C++
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
introduce yourself and why you want to work at apple
How experienced are you with TCL? What needs to be done before sending a design out for fabrication?
Design, Test plan, SystemVerilog ......
Digital questions, UVM environment based questions
What is crosstalk? Ways to fix crosstalk? Relationship between Resistance/Capacitance to Length & Width What is charge sharing? How to fix? What is body effect? What is short channel effect? List several effects.
Explain what you learned in this course (VHDL, design classes, object oriented programming, etc)
Asked about Basic Signalling like Block Section Working, Logic Circuits, Control Table Checking, Signalling Plan, CBTC Principles, Automation in C#, Process Automation & outcome. Success Ratio & feasibility of Automation in Signalling
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