1)Should be ready to write some logics (C/Verilog/System Verilog) on the spot . 2)Blocking and Non-Blocking. 3)Fork/join types and applications. 4)Test bench architecture blocks.(asked to write a generalized code to implement gen and bfm).
Verification Engineer Interview Questions
2,556 verification engineer interview questions shared by candidates
There are three boxes, one contains only apples, one contains only oranges, and one contains both apples and oranges. The boxes have been incorrectly labeled such that no label identifies the actual contents of the box it labels. Opening just one box, and without looking in the box, you take out one piece of fruit. By looking at the fruit, how can you immediately label all of the boxes correctly?
Rewrite UVM phasing.
What do you know about ARINC 429 protocol in terms of railways security. Rolling stock knowledge etc.
power management related?
There are two large arrays filled with random 64-bit signed numbers. How do you determine what are the common numbers in the arrays? Give an algorithm that is linear in complexity. You can use unlimited memory.
An arbiter with an asynchronous reset receives four requests signals, R1, R2, R3, R4 and generates four grant signals, G1, G2, G3, G4. Request R1 has the highest priority and request R4 has the lowest priority. Draw the state diagram.
Mostly on Digital systems design, fsm's, timing analysis and computer architecture.
Design an logic circuit to generate a pulse on an input change from low to high (edge trigger).
Big O for binary search.
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