SystemVerilog basic OOP
Verification Engineer Interview Questions
2,556 verification engineer interview questions shared by candidates
What's the disadvantage of having a cache with more associativity?
Coding problem was a graph algorithm related one to be resolved in an hour on a video call with several engineer on the other side providing feedback
Synchronize two systems with different clocks? Write code verilog
1 is heavier than the other 5 marbles among 6 mables . given a weight to find the heavier one.
implement a machine that count number of 1's in a 8 bit input
What are the five stages of a classic RISC pipeline?
explain setup and hold time with figure and some example and then interviewer added some circuitry and asked to solver setup and hold violation in circut
The questions were : write a SV code to get unique random numbers, rand vs randc, write driver code etc.
2. Generate two arrays of length 10, whose elements are unique to each? Later he explained that all the 20 elements in both the arrays should be unique
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