Why there is a E stage in MESI protocol, I said I don't know, will you please teach me that? He said, NO.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
How do you implement RAM in C++?
Q: 5 ways to write a function that if receives 4, it returns 7 and if it receives 7, it returns 4.
A packet with address, and data. The address range is split into 4 regions. Create a class that will generate 100 packets and cover all possible ranges.
What conflict is possible when you have a weak memory model and another memory location containing flags that indicate the status of another memory location (described above)
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
asked in system verilog and UVM
Technical questions related to digital design, based on projects from your CV and verification languages, methodologies. Questions were basic ones and there were a few scenario based questions too.
Technical questions related to job role
Name last job experience and some other questions
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