Do you know system verilog
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
Stack, heap, computer architecture related questions. Cache coherence.
C++ Questions, memory allocation
build a 8 to 1 multiplexer with 2 to 1 multiplexer. use minimal number of components
Walk through the CV and deep dive the previous project technical details. Many general questions related to verification methodology.
1. explain college project
What I know about verilog
they ask me my preference of work
Second interview question: Given the following assembly commands: MOV Ri <-- Rj/immediate (put register j or immediate value into reg i) INC Ri (++) DEC Ri (--) JNZ Ri (jump not zero) 1. Code an assembly program that calculates x*y where x and y are unsigned integers 2. What values of x and y will cause the program to fail? 3. Modify the program to deal with these values 4. What result will we get if we run the program with values from question 2 and no modification from question 3? 5. Is it possible to answer question 1 without MOV command? Prove it!
Describe memory BIST architecture, march algorithm, MATS test. String parsing questions to process/filter verilog code encased in ifdef/ifndef. How to set up testbench for, and maximize test coverage for scan debug verification. The engineering manager whom I ate with, asked me for my ethnicity. Although I grew up in California, he kept trying to connect with the interests of his neighbor, who happened to be of the same ethnicity. The questions were along the lines of "My <ethnicity> neighbor, they like to play tennis. Do you like tennis? Do you follow this tennis player from <my country of origin>?"
Viewing 491 - 500 interview questions