Some digital questions and verilog
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
In SV and UVM started with basics and went deep while process is going on
They mostly concentrate on your resume , computer architecture and digital design basics
Salary negotiation. Do not hesitate to ask more than industry standard, no matter what is your current CTC
The asked me to write a C program that print an infinite number of the Fibonacci series.
Design a circuit for edge detection circuit
What is D-Day?
have you done army. how much payment you want. when do you want to start if we take you.
Who ancient Greek philosopher didn't write any of his works? ,
was eager to know about the previous company workflow
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