1) Swap in Verilog 2) Print 2D matrix spirally starting from centre 3) randomize the size of a 2D matrix/multi dimentional array 4) Fork-join and how to disable fork 5) Assertions 6) Reverse a string 7) How to verify a vending machine 8) Application of UVM Barrier class, 9) Divide by 5 state machine and extract a mathematical equation to generate the next state , 10) Write a system verilog test to verify if all the clocks on the SOC have been switched off after writing 'b1 to a register , 11) Why do we need UVM agents , 12) How is UVM Scoreboard implemented, 13) Constraint address to word accessible , atleast 2 ways to do it , 14) Test Plan and functional Coverage
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
What role you want to be in 5 years.
Write UVM Monitor for the defined case.
They asked me about my work experience and the day to day activities in my present company.
They gave me few written programmes and asked me to explain the programme flow
Can u join us aaand give me money. We will train you and then give u job.
SV UVM based question, purpose of uvm_config_db, uvm testbench architecture
Can I give me 75000, I can train and give u job
First round of documentation Share a set of documents to enable us to roll out a competitive offer. List of documents Your HR single point of contact will share the list of documents required for submission
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