Tell me your personal advantages and disadvantages.
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Unexpected question was string manipulation using C++. Since I have not used C++ for strings since I have started working and it is not a hands-on question that has anything to do with the technical expertise of the person, it was kind of unexpected.
SystemVerilog basics and UVM basics
1. Explain your minor project. 2. They focused on Digital Electronics and Verilog coding skills 3. Aptitude questions 4. Some computer architecture questions
dld, verilog, sv, uvm, protocols
What are the problems you faced when interacting with the client?
what is the flow of UVM methodology, and structural view of verification ?
related to the offered role skills
Write driver code for AHB protocol
basic SV questions
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