Write the VHDL or Verilog code for a given state machine diagram.
Verification Engineer Interview Questions
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One of them asked about very fundamental elementary questions which was hard to recollect
There was no really difficult question. If I remember clearly, maybe questions on RTL coding style, like always @(posedge clk, reset_active) begin if(reset_active) do somthing else do something end vs: always @(posedge clk, reset_active) begin if(!reset_active) do something else do something end What is the difference in above two impl's.
A basic testplan scenario
At one point, I was asked if I would go to the customer in Texas. It sounded to me like the interviewer was talking about a single trip. I should have asked how much time I would spend in Texas. Later, when the offer came, they wanted me to spend one week out of every month in Texas.
Linux mount filesystem
Diffcult
it was general discussion about logic design and he gave me discribtion about circuit and asked me to leocate the signals that i should select for testing and verifying they gave me small task about an alu and i am supposed to write verification code in system verilog for it , actually they were very generous they provide the matrials to learn more about system verilog and how to write such a design
Coding questions were on Constraints and Assertions.
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