What's your name , is it [name] ?
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
implementation of driver class based on the figure they gave
Discussed about verification projects in resume, how is formal and functional verification different. On coderpad, he gave an RTL code and asked to identify different scenarios and write SV properties of them. The RTL had a buggy FSM and asked me to debug it.
Tell us more about your experience
UVM based questions and Assertions and constraints
Write a SV model for comparator
Create a 4-to-2 priority encoder using only basic logic gates. Then use those encoders and MUXs to create a 16-to-4 encoder. Create a state machine to show if a binary number is divisible by five.
Assertion to check the waveform
What is the difference of function and task in verilog
Q. Describe your test plan for a FIFO
Viewing 2121 - 2130 interview questions