Only behavior questions, nothing technical
Verification Engineer Interview Questions
2,562 verification engineer interview questions shared by candidates
Past experience Projects and day to day work Some SV UVM questions
Implement a 4-bit counter in SV.
They repeatedly asked about how I handle stress
Design a finite state machine for a specific control scenario and explain your verification approach.
Indepth questions for AXI protocol
Q1: I was asked about the basic working of caches Q2: I was told to explain about virtual memory Q3: I was given a cache configuration and was told to identify if I this can be a VIPT or VIVT cache.
* find if a string is a palindrome
Give examples of how loops work in ARM?
Draw internal cmos crcuit for nand, nor gates. Bandwidth of opamps. Solve basic opamp circuits. They focus more on fundamentals of both analog and logic design. Also focussed on vhdl as it was used a lot for modeling in that group.
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