Implement a state machine that detects modulo 5
Verification Design Engineer Interview Questions
951 verification design engineer interview questions shared by candidates
Why should i hire you?
Basic stuff about Verification and assertions
How would you do your job in X project?
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is the difference between Mealy and Moore machines?
Uvm phasing process, different phases in uvm
What will you do if you made a big mistake?
write code which returns error if we got 10 packets within 10 seconds
DSP, OOPs Concepts, Basics CMOS based concepts
Viewing 751 - 760 interview questions
See Interview Questions for Similar Jobs
Fpga Design EngineerVerification EngineerRtl Design EngineerVlsi Design EngineerLogic Design EngineerPhysical Design EngineerCpu Design EngineerElectrical Product Design EngineerSenior Vlsi Design EngineerSenior Fpga Design EngineerVerification ManagerSenior Asic Fpga Design EngineerApplication Design EngineerHardware Design EngineerSenior Physical Design EngineerIc Design EngineerFpga Development EngineerAsic Verification Engineer