What is an Agent? Passive vs. Active.
Verification Design Engineer Interview Questions
952 verification design engineer interview questions shared by candidates
what is Synchronous reset and asynchronous reset?
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
what is function overriding and overloading
Draw the circuit base on the coding provided
Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
Tell me about yourself. Do you mind to relocate?
every details on uvm, some coding question and data structure
You are given a string that contains numbers, the arithmetic operators +, -, *, /, and various types of parentheses. Design and write pseudocode for a function that evaluates the expression and returns its numerical result.
show how code coverage and function coverage works. explain with code
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