How do I reduce power at the system level?
Verification Design Engineer Interview Questions
952 verification design engineer interview questions shared by candidates
Design a mod 5 counter
design mod 4 counter using T flipflop design a fulladder using logic gates
1. What is actually happen from moving the mouse physically to the the cursor moves? 2. Follow up the question 1, asking you to explain some OS questions, like what is interrupt.
Basics of digital, verilog, system verilog and uvm.
First there was some basic questions on Computer Architecture, Verification Concepts and RESUME. After that she asked me to write code for hamming distance in prefered lang and UVM Code for driver component.
Given this design and their features, explain how you would build a UVM testbench to verify it.
What is a state machine?
A router transmits the data. If the data is destined for same address then the packets should arrive in the same order as it is transmitted. The packet sent second is not allowed to overtake the one sent first. But if the packets are destined for different address it can overtake the other packet. How will you verify this design. The packet does not contain any ID.
What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.
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