Basic RTL Design related concepts, SV UVM basic concepts, writing scoreboard.
Verification Design Engineer Interview Questions
952 verification design engineer interview questions shared by candidates
Question about digital design and system verilog and uvm related questions
1st phone interview: Basics of Verilog. Explanations for different projects on resume. 2D array containing image data, how will you rotate the matrix to rotate the image by 90 degrees clockwise? try to use least memory(i.e) rotate and store in the same input matrix.
power integrity understanding: including impedance threshold define and theory.
implement 4-2 priority decoder to 16-4.
They asked about mu uvm design verification project
pipeline processor architecture, hazard, shared memory problem, cache issues—remote repeated words both in SystemVerilog. I answered how to do it in python, but he insisted Con using c or SystemVerilog. In the last question, he asked me why I choose design verification. The whole procedure lasts about 53 minutes, quite tense I would say. I did not answer the memory coherence and delete repeat words in C. I would say I did not do it well. Hoping this could help others to get job. Just preparing questions.
Memory allocation
1. FSM to check if a number is divided by 5. 2. Implement basic logic gates using a MUX and NAND. 3. Reverse a linked list. 4. Questions about a FIFO
Questions mostly about the project. Basics of Pcie protocol
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