Resume questions, fifo questions, assertions, coverage
Verification Design Engineer Interview Questions
951 verification design engineer interview questions shared by candidates
General questions in Python, C, Verilog, and SystemVerilog.
1. About the company, why apple 2. About projects as per resume-interesting test case, negative test case 3. different types of Hazard and how to avoid those 4. pipelining concept 5. Problem-solving: (using associative array-)how to sort names without repetition
CDC, HW design, testbench engineering, etc..
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
There was no tehnical interview for no experience engineer
SV, UVM, Driver sequencer handshake mechanism
How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.
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