About system verilog , verilog, digital electronics
Verification Design Engineer Interview Questions
951 verification design engineer interview questions shared by candidates
Sorting, bit logic
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
class A; function int foo(); int a; return ++a; endfunction endclass program tb; A a; int b, c; initial begin for(int i = 0; i < 10; i++) begin b = a.foo(); c = foo(); $display("B = %0d", b); $display("C = %0d", c); end end function int foo(); int a; return ++a; endfunction
design question - design a system to identify if input bitstream is divisible by 5 - taking a 16bit stream, programming - print matrix spiral, etc. Also assertion questions, UVM
Tell me a bit about yourself.
Immediate vs. Concurrent Assertions .
What is a pipeline driver?
I shared my experience in the projects that I worked on so far.
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