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Verification Design Engineer Interview Questions
951 verification design engineer interview questions shared by candidates
build a 8 to 1 multiplexer with 2 to 1 multiplexer. use minimal number of components
What I know about verilog
A packet with address, and data. The address range is split into 4 regions. Create a class that will generate 100 packets and cover all possible ranges.
What conflict is possible when you have a weak memory model and another memory location containing flags that indicate the status of another memory location (described above)
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
Verification plan for a given scenario, what are the possible ways we can verify.
What is the difference between calloc and malloc?
They asked: blocking, nonblocking statement, asked to write a code for a given circuit, then they asked about asynchronous, synchronous reset, how and where they are applied. In second round, they asked question based on processor design, FIFO, STA.
Phases in UVM, previous work experience and SV questions
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