Hold and setup time, FSMs
Soc Interview Questions
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STA, CTS, Floor planning, Logic Circuits, PNR 1. What is OCV and derate factors 2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors) 3. How to reduce setup violations and hold violations? 4. Difference between H-tree and Mesh? 5. Techniques to reduce clock power? 6. Low power design techniques 7. What is Multi Bit FF? 8. Draw basic logic gates (And) using NOR (NAND) gates? 9. Crosstalk glitches? 10. Placement of macros questions 11. How to calculate channel spacing between macros/ 12. SRAM design questions 13. Physical only cells- Tap cells, Tie cells use and where do we place them 14. How Delay of a net/cell changes with VDD/ 15. Capacitance and Resistance of wire effects on delay and how to reduce it? 16. How to reduce static, Dynamic, short -circuit power? 17. Where to use LVT, HVT cells? 18. Difference between local skew and global skew? 19. Verilog Coding question- Synchronous and Asynchronous DFF 20. What is the use of End cap cells and Decap cells?
What would be your first approach to a Ransomware attack?
What's the msot interesting security incidents you have worked on?
Quelles sont vos compétences?
Why we need to hired u? Please convince us.
Preguntas técnicas sobre seguridad en general.
Have you had issues dealing with people coming back at you over the phone, if so, how did you calm the situation and handle that person?
Some system verilog Questions
Draw an XOR out of NAND gates, logic minimalization, draw FSM for given signals and how many flip flops are needed to implement the design?
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