First interviewer did bus connection verification. so he asked about the protocol of ahb and axi. Then he asked how many vip should be used for their verification environment. I didn't understand the question clearly. Because if we want to keep CPU and the code run on real CPU, we don't need to replace these interfaces with VIPs, but if the CPU needs to be replaced, only other slave/master interfaces need to be replaced by VIPs. After he cleared it, what he wanted to do was to replace all the CPU interfaces and other IP interfaces. The second interviewer asked 2 questions: 1) how to check the module was reset by reading/writing registers? The premise for this was there was no spec for register. 2) how to check an interrupt was generated? There was a bit in the register for the interrupt signal. The third interviewer asked the following questions: 1) virtual memory structure 2) spin lock 3) tomasulo 4) fibonacci generator The last technical interviewer asked: 1) shell questions: search a key word in a file and count how many lines contain the key word 2) Perl sort question: user perl to sort a hash with key or with value 3) set environment variable in Perl 4) fibonacci generator 5) there are 2 buckets: 5 litters and 3 litters, how to get 4 litters of water 6) there is a rectangle pie, remove a small rectangle in that large rectangle, after that, use a straight line to cut the pie to get 2 equal areas. There was another question I forgot who asked: use SystemVerilog to generate address with the following constraint: 0x0 (mem1), 0x4(mem2), 0x8(mem3), 0xC(mem1), 0x10(mem2), 0x14(mem3) ...
Soc Engineer Interview Questions
191 soc engineer interview questions shared by candidates
Was asked about questions related to my projects. And topics related to timing analysis, digital electronics, computer architecture etc.
1. What motivates and frustrates you? 2. Many coding questions
Glitch free clk switch design
Describe logic gates AND, OR, XOR
Since the company has a scientific business among other things, I had to convince them that I was actually interested in and figuring out the technologies of the future.
The basic RTL coding such as non blocking & blocking.
1. Static timing analysis q. setup/hold , FF , latch
How to swap two registers in verilog without using third register?
Different multiplexer and demultiplexer and describe the function application.
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