Static timing analysis (writing max, min delay, multi cycle path, false path), clock domain crossing (for 1-bit, multi bit), Coding questions, questions on previous projects
Soc Engineer Interview Questions
191 soc engineer interview questions shared by candidates
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
Asynchronous FIFO, Setup/Hold time, CDC, reset
Write a test plan for asynchronous reset flip flop
Asking abut the technical question.
Design a clock divided by 3. Design a synchronous FIFO, Sequence Detector
Questions on how to micro-architect linked list memory
Can you cope up with the demanding work hours and different responsibilities of the role?
Asked some digital logic problems
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