how to you put synchronous and asynchronous reset in your code? what is the pros and cons of both situation.
Rtl Design Engineer Interview Questions
185 rtl design engineer interview questions shared by candidates
how do you perform floating point addition in hardware?
If the incoming data to the FIFO is 1Mhz and outgoing data is at 1Khz and the data is 32 bits wide, what would be the depth of the FIFO?
How is organized a CPU?
ASIC design processes, techniques, design processes
Async fifo design and SDC contraints for it. Pulse synchronizer cross clock domains.
latch vs FF
Basics of digital K map based questions Verilog programing some logical ability questions
rtl basics questions digital design
Tell me about yourself.
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