Basic Digital Electronics questions related to counters
Rtl Design Engineer Interview Questions
185 rtl design engineer interview questions shared by candidates
hello how are you?
question about architectures, questions based on cv, why you want to work for imagination.???
Caches
mealy and moore state diagram sequence generator, question regarding course project
Fixed priority arbiter, Arbiters(4 clients 2 with fixed priority and 2 with round robin), FSM(sequence detector, Lift Controller), How to change reset value of register during an ECO
1. Given a set of specifications for register elements , how do we compute the maximum frequency of operation? 2. What are the different types of constraints used in design , when and how are they specified?
1. Counters 2. CDC and type of Synchronizer 3. Sync FIFO
Basic RTL codes and degital design,fsm state digram(melay andMoore state machine).setup and hold time.latch and d flip flop.synchronous vs asynchronous fifo.syncronohs reset and asynchronous reset verilog code .static timing analysis
how to you put synchronous and asynchronous reset in your code? what is the pros and cons of both situation.
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