sync vs asyc rst
Rtl Design Engineer Interview Questions
185 rtl design engineer interview questions shared by candidates
Most questions were from digital electronics and verilog
Design a module to return trigonometric sine value. Other question is related to the designing of the State Machine with the specified requirements.
Mainly related to best techniques for hardware design and algorithms
Do latches have Metastability?
What is the difference between latch and flop?
Based on memories, digital design, Verilog coding
Explain each state in a mesi protocol.
Software (OOP, efficiency, data structures), Computer Architecture (cache coherency, pipelining), Logic (k maps, simplifying boolean expressions), and Verification (coverage, how to test, previous experience)
Difference bw asynchronous and synchronous circuits Propagation delay Static and dynamic delay
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