FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
Low power implementation - UPF Level shifters, isolation cells, retention cells, clock gating, PoR sequence etc.
Hiring managers asked about project details and tools. He was expected digital design solutions and CDC related topics. Lint and Lowpower design questions asked and given FIFO calculations. Current company job roles and responsibilities and challenges in current project
What's hash? what's link list?
What's setup and hold time? How to solve the setup and hold violaton.
another tough question was that you are given a small design, you are asked to tell how you test that logic. like how/what checkers to implement.
FIFO depth
nothing as such..everything was from what i had studied in BS and MS
Explain and design a two level branch predictor
I could not reveal the questions
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