What is important when considering power gate placement?
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
all questions were straight forward
Not much. mostly about what I did in previous projects
What software you use for synthesis
About cmos , STA,Physics of VLSI, but written test is tough, if ur done with written more probability of getting
Noise margin in CMOS, Regions of operation in CMOS
Told to design a layout through a very slow laptop, be prepared. asked about parasitics in layout design, and effect of high voltage on MOS and what should you do.
Previous challenges as a physical design engineer, lot of questions about the .libs and encounter commands.
1. project experience 2. technical questions related to PD
Draw Full and half adder circuits. Draw a 4-bit adder circuit. Draw 2 state counter. Draw NAND gate using CMOS. What is logical effort? What are LVT cells and how does leakage is affected using them? Solving some Gate-based and Boolean algebra-based questions.
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