Tell me about your Self and Synthesis, STA Technical Questions. Timing Closure on Block and Chip Level.
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
What is JTAG What is cluster based design? Describe about cluster based region? 2. What are the problems are faced when placing long net of FF to FF path and Short net of FF to FF path? 3. Is timing driven placement advantageous over the functionality based placement? Explain briefly. 4. Explain In Place Optimization and Timing Delay? 5. How to do Congestion optimization and balance slew?
They asked me mainly about digital circuits and in VLSI the emphasis was mainly on cmos technologies
Digital electronics, synthesis, physical design and Linux commands and tickle, if any scripting languages related to hardware language
Design an asynchronous mod 6 counter
Do you have some problems with APR? Can you tell me how to solve it?
CMOS, AND Gate using inverter circuit
Asked about PnR, STA and PV
Most of the questions are related to sta
Analog basics and few sta questions
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