What is clock domain crossing?
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
Draw Cmos inverter.What would happen if we swap Pmos and Nmos.What if Nmos is connected to VDD. Questions regarding .lib,LEF, Antenna file content . How do we define rectilinear polygon in LEF.. Multicycle Path calculation for setup and hold . Draw 4 Input NAND Gate using 2 -Input NAND Gate what is index table defined in .lib file. How do we define antenna rules in techfile What are all challenges faced in your recent project. Questions were more from your resume. Any scripting which is hard for you. Tell us more about colored flow.
Draw a layout for a NAND gate
Algorithm / heuristics for a routing problem. An exact solution isn't needed, but just the ideas
how to synchronize two blocks controlled by different clk signal
pd flow and pd design
What is Set up and hold time? How would you solve set-up time issues? Why do set up time issues occur in a circuit? Theoretical questions based on Setup time were asked to solve. How does setup time vary with respect to the PVT? What does "7nm" in 7 nm technology represent? How would you increase the buffer strength? Theoretical question based on cache and miss rate and virtual memory was asked to solve. What is cross talk? How to prevent it? A puzzle based on Bullet and gun?
Set up time and hold time constraints
implement a flip flop from muxes ...
VLSI basics and CMOS device operation
Viewing 281 - 290 interview questions