Once you clear the written test which you might get to know within a week after the test, then there would be a skype interview. Interview focus is mainly on your projects or internships. low power techniques, STA, How to fix setup and hold violation in a design and cmos related questions.
Can you explain common centroid layout?
1. What is setup and hold time? 2.Operation regions 3. Vlsi design flow 4.Questions related to MOS Circuit
ASIC design flow along with TCL
Some basic knowledge of C++
T setup and t hold equations State machine that finds the following state and outputs one: 01011 Represent the function f = (abc’)’ using just MUXs and 1s and 0s
Have you built a library before
They asked me three questions. the third one-give us the minimum number of digits needed to create sums from 1 to 120
they asked me about timing, questions about setup time and hold time. like what you can change that reduce the risk of setup violation. or where you put the registers to reduce the risk of set up violation
Questions about projects. Physical Design basics, from floorplan to signoff. Setup and hold time. Multi-corner STA. CMOS basics. Given a CMOS circuit gives the operation region each transistor is operating on.
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