How to modify a two-input NAND gate to an inverter?
Physical Design Engineer Interview Questions
594 physical design engineer interview questions shared by candidates
1. project related 2. cpu related
Difference Between SRAM and DRAM
What are setup and hold time
1. First and foremost be clear about your project work and internship work because this is the first question which they asked. 2. questions were mostly from my resume and whatever skills I had mentioned. 3. Questions were related to Timing constraints, Cross-talk, how to fix cross talk issues, Timing DRC's and Setup and hold violation. 4. difference between Physically and logically exclusive clocks? 5. What information is there in .lib file and what is a SPEF file and what it contains? 6. what inputs are required to fire STA Run ? 7. If you have worked on any tool like primetime or ICC then you can expect some questions related to commands. 8. some basic UNIX commands like grep, sed and awk related questions and some scripting related questions. 9. latch up issue and body effect , and how it affects and how can we fix up these issues? 10. questions were related to clock gating and power gating.
most of the questions from digital crkts and few from C lang.
Draw the state diagram of the TAP controller in JTAG
What is the effect on delay when an inverter input is connected to 10 inverters and output is connected to a few more inverters?
You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup, T_hold, etc. How to determine the cycle time and hold time of this circuits.
if the problem is X-talk, how do you suggest to fix it?
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