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Physical Design Engineer Interview Questions

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595 physical design engineer interview questions shared by candidates

1. what is the max freq of a given circuit.(setup and hold analysis related) 2. one question was related to stuck at fault. we need to find out the input test pattern in order to detect the stuck at fault of given circuit. 3. IN1?A:IN2?B:IN3?C:1'b0 How many 2:1 mux are required to implement this? 4 one question was related to FIFO Depth calculation. 5. In a given circuit to meet timing how many no of re timing flops need to be inserted?(you should be clear with setup analysis) 6. Questions were related to transistor sizing and cache memory hit and miss ratio. 7. One puzzle was also asked of Annual function and van related(don't remember exactly. :p)
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Staff ASIC Physical Design Engineer (ASIC PD Engineer)

Interviewed at NVIDIA

4.4★
Jan 16, 2021

1. what is the max freq of a given circuit.(setup and hold analysis related) 2. one question was related to stuck at fault. we need to find out the input test pattern in order to detect the stuck at fault of given circuit. 3. IN1?A:IN2?B:IN3?C:1'b0 How many 2:1 mux are required to implement this? 4 one question was related to FIFO Depth calculation. 5. In a given circuit to meet timing how many no of re timing flops need to be inserted?(you should be clear with setup analysis) 6. Questions were related to transistor sizing and cache memory hit and miss ratio. 7. One puzzle was also asked of Annual function and van related(don't remember exactly. :p)

you have 2 types of balls, red and white, you have 3 boxes 1 with red balls, 1 with white balls, 1 combined. the boxes are labeled with stickers. the stickers are not correct! one box marked as "red" second box is marked as "white" third box is marked as "combined". how many tries you need to know which box is realy the red,white and combine.
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Physical Design Engineer

Interviewed at Intel Corporation

3.9★
Dec 21, 2018

you have 2 types of balls, red and white, you have 3 boxes 1 with red balls, 1 with white balls, 1 combined. the boxes are labeled with stickers. the stickers are not correct! one box marked as "red" second box is marked as "white" third box is marked as "combined". how many tries you need to know which box is realy the red,white and combine.

Basics, everyone is interested to know depth of your knowledge so for graduates they will start from CMOS transistor level and keep going higher to SoC design level. As along as you could break, its ok to say if you don't know about something, they are interested to see where you got broke and measure depth of your knowledge. One advice to all graduates keep your fundamentals clear, that brings confidence and vlsi industry respects people who have knowledge.
avatar

Physical Design Engineer

Interviewed at Intel Corporation

3.9★
Mar 13, 2017

Basics, everyone is interested to know depth of your knowledge so for graduates they will start from CMOS transistor level and keep going higher to SoC design level. As along as you could break, its ok to say if you don't know about something, they are interested to see where you got broke and measure depth of your knowledge. One advice to all graduates keep your fundamentals clear, that brings confidence and vlsi industry respects people who have knowledge.

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