Hardware Engineer Ii Interview Questions

32 hardware engineer ii interview questions shared by candidates

Manager kept saying questions could be answered by a "5th grader". Very vague instructions on how to answer the questions. 1. Find a number missing from different numbers. Had to use multiplication and division. 2. Design a pulsing circuit using digital to double the frequency. 3. How many tries to find the heaviest weight on a scale (1) when there are 9 weights in total.
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Hardware Developer II

Interviewed at Oracle

3.5
Oct 7, 2022

Manager kept saying questions could be answered by a "5th grader". Very vague instructions on how to answer the questions. 1. Find a number missing from different numbers. Had to use multiplication and division. 2. Design a pulsing circuit using digital to double the frequency. 3. How many tries to find the heaviest weight on a scale (1) when there are 9 weights in total.

Basic RTL questions on FSMs, full VLSI flow from synthesis to gds, clock gating, SRAM internal circuits, STA timing questions, inverter and buffer characteristics, low power methodologies, NAND gate implementation of gates and timing and layout
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Hardware Developer II

Interviewed at Oracle

3.5
May 20, 2016

Basic RTL questions on FSMs, full VLSI flow from synthesis to gds, clock gating, SRAM internal circuits, STA timing questions, inverter and buffer characteristics, low power methodologies, NAND gate implementation of gates and timing and layout

Phone inetrview , they majorly targeted my resume (Skills , projects, previous work experience). Did ask a few logic design questions setup hold, nand gate etc. Onsite was not that bad asked on Sync/Asyns FIFO design (had to write verilog code- explain corner cases), state machines (detect a sequence), 4-5 Puzzels, Verilog questions.
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Hardware Engineer II

Interviewed at Cisco

4.1
Oct 24, 2014

Phone inetrview , they majorly targeted my resume (Skills , projects, previous work experience). Did ask a few logic design questions setup hold, nand gate etc. Onsite was not that bad asked on Sync/Asyns FIFO design (had to write verilog code- explain corner cases), state machines (detect a sequence), 4-5 Puzzels, Verilog questions.

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