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Fpga Verification Engineer Interview Questions

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25 fpga verification engineer interview questions shared by candidates

Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.
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FPGA Verification Engineer

Interviewed at Ciena

4.1★
May 7, 2014

Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.

This was an entry level position. Basic questions were asked about FIFOs and metastability. Then I was asked to code an RTL Design for an Ethernet cable. Had to dissect packets of data and extract the payload while discarding everything else.
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FPGA Verification Engineer

Interviewed at SpaceX

3.8★
Mar 11, 2025

This was an entry level position. Basic questions were asked about FIFOs and metastability. Then I was asked to code an RTL Design for an Ethernet cable. Had to dissect packets of data and extract the payload while discarding everything else.

1. 30 mins phone screening about my resume and my background. 2. a) fill out a truth table for 4 to 1 mux. b) implement an 8 to 1 mux with 3 given 4 to 1 mux. c) 1)Given few declared variables in a struct C/C++, calculates the total number of bits that allocate and occupy in the memory. EX. ..... char hello; uint_32 hi[5];....... ANS: total bits of memory require = 8 + 32 * 5 = 168 bits. 2) Imagine that an HDL code is sending 168 bits of data to the two variables in struct C/C++. Fill out the bit length of each variable. ANS: hello[7:0] and hi[167:8]. Very easy questions.
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FPGA Design and Verification Engineer I

Interviewed at HPR

4.2★
Aug 7, 2021

1. 30 mins phone screening about my resume and my background. 2. a) fill out a truth table for 4 to 1 mux. b) implement an 8 to 1 mux with 3 given 4 to 1 mux. c) 1)Given few declared variables in a struct C/C++, calculates the total number of bits that allocate and occupy in the memory. EX. ..... char hello; uint_32 hi[5];....... ANS: total bits of memory require = 8 + 32 * 5 = 168 bits. 2) Imagine that an HDL code is sending 168 bits of data to the two variables in struct C/C++. Fill out the bit length of each variable. ANS: hello[7:0] and hi[167:8]. Very easy questions.

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