Questions on what projects have you worked on, some technical questions of synthesis and timing of digital design.
Fpga Engineer Interview Questions
542 fpga engineer interview questions shared by candidates
Two data lines with same numbered packets arriving in order but not synchronized. Make sure you only send the packet once and discard the latest same packet to arrive.
Un problema de razonamiento lógico
Write an RTL Block that implements 4x4 matrix multiplication. then they asked me to optimize the critical path. Then what if the elements are floating point numbers? Then check if we can reduce the chip area using less number of Multipliers.
All digital basics and verilog coding
FPGA design flow. function vs task,basic debugging questions,UART design flow,SPI design flow
logic optimization. design algorithm to reduce redundant circuit. share result of logics.
1. Design a divider
First onsite interview: - Showed me a Stratix Altera FPGA ALM and asked what is it, which manufacturer and which model - Same but with a Xilinx one - Asked me to explain a document regarding some state machine explanation by Altera - Showed me an Altera transceiver schematic and asked me to explain it and detail each block of it - Showed me a general schematic of an FPGA and asked me to define each hard block that was present on it - Showed me a diagram of CVP (Configuration via Protocol) from Altera and asked to explain it
Describe the function given a specific digital circuit diagram.
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