2. What are the Channels in AXI Interface?
Fpga Engineer Interview Questions
542 fpga engineer interview questions shared by candidates
4. What is the difference between Signal and Variable in VHDL? And Blocking and Nonblocking in Verilog?
Fourth onsite interview: - Explain me the metastability - How can you cross different clock domains - Explain me how a FIFO does work and how is it built Fifth onsite interview: - Reasoning questions. Too much complicated to explain by text, sorry guys!
A problem based on setup time, holdtime for given flip-flops.
how to swap 2 values stored in 2 registers using verilog. - how to do it in one clock cycle.
Design Asynchronous Fifo Timing Analysis Setup and hold time
how to implement a derivator
How is your experience related to this position?
cité moi un type de exemple de FPGA
How would you send a signal across clock domains from a fast to a slow domain.
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