What is a challenging situation that you experience in a group project?
Fpga Design Engineer Interview Questions
138 fpga design engineer interview questions shared by candidates
Asked about setup time, hold time violations of different circuits and also about clock domain crossing.
Technical question : questions about HDL languages as well as clock domains.
Multiple SystemVerilog questions were asked. No questions about VHDL were asked.
Can't remember.
What you know about the company
They asked to explained me something from my resume that matches the skills of the job description.
C++ and verilog, fpga questions
Walk through past designs, clock crossings, some scenarios just the usual but nothing that was out of line for the position
Questions related to CDC and Verilog/VHDL. one behavioral question. Questions from the resume.
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