Digital Verification Engineer Interview Questions

43 digital verification engineer interview questions shared by candidates

In round 1 - 19 MCQs related to general concepts, a mix of digital and analog electronics, mainly digital. 3 subjective question from - STA, STA, FIFO depth calculation 2 circuit design questions - FSM sequence generator , differently clock delayed output using MUX and flip flops. Round 2- Started with basic STA questions and went up to solving some on paper. Later digital design questions about mux , flip flop, counter, clock divider , FSM. Basic Verilog code like Fibonacci numbers generator , counter. MOS - MOS inverter questions and sub threshold region conduction. Short channel effects.
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Digital Design Verification Engineer

Interviewed at NXP Semiconductors

4
Oct 30, 2022

In round 1 - 19 MCQs related to general concepts, a mix of digital and analog electronics, mainly digital. 3 subjective question from - STA, STA, FIFO depth calculation 2 circuit design questions - FSM sequence generator , differently clock delayed output using MUX and flip flops. Round 2- Started with basic STA questions and went up to solving some on paper. Later digital design questions about mux , flip flop, counter, clock divider , FSM. Basic Verilog code like Fibonacci numbers generator , counter. MOS - MOS inverter questions and sub threshold region conduction. Short channel effects.

it was general discussion about logic design and he gave me discribtion about circuit and asked me to leocate the signals that i should select for testing and verifying they gave me small task about an alu and i am supposed to write verification code in system verilog for it , actually they were very generous they provide the matrials to learn more about system verilog and how to write such a design
avatar

Digital Verification Engineer

Interviewed at Si-Vision

3.6
Aug 13, 2020

it was general discussion about logic design and he gave me discribtion about circuit and asked me to leocate the signals that i should select for testing and verifying they gave me small task about an alu and i am supposed to write verification code in system verilog for it , actually they were very generous they provide the matrials to learn more about system verilog and how to write such a design

Tips for round 2- keep your basics strong. Don't need much. Just got get played by interviewers. If you're stuck or don't know the answer. Atleast try for an approach and keep asking for feedback. Before solving any question, explain your approach and then proceed. Your behaviour shouldn't be like digital systems, either 0 or 1. It should be like analog. Keep explaining every step. And don't say anything that you can't explain. Tips for round 3- Just don't lie. Speak the truth. Don't mention GATE scores in CV. Deny any further studies plan from your side. Just say that you'll do it if your firm wants you to upgrade your skills and be more productive for firm. Else you have no plans. Preferred location - Always say Noida.
avatar

Digital Design Verification Engineer

Interviewed at NXP Semiconductors

4
Oct 30, 2022

Tips for round 2- keep your basics strong. Don't need much. Just got get played by interviewers. If you're stuck or don't know the answer. Atleast try for an approach and keep asking for feedback. Before solving any question, explain your approach and then proceed. Your behaviour shouldn't be like digital systems, either 0 or 1. It should be like analog. Keep explaining every step. And don't say anything that you can't explain. Tips for round 3- Just don't lie. Speak the truth. Don't mention GATE scores in CV. Deny any further studies plan from your side. Just say that you'll do it if your firm wants you to upgrade your skills and be more productive for firm. Else you have no plans. Preferred location - Always say Noida.

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