Cross clock domain synchronization - Module A transmits @ 100 MHz and Module B accepts at 10 MHz. How will you manage the transactions?
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
1st two interviewers : Volatile v/s Non Volatile memory (RAM/ROM) Basic Verilog questions like blocking v/s non-blocking, continuous vs procedural etc Explanation of all my FPGA/Verilog-related projects 2:1 MUX using basic gates Setup vs Hold, which is more important, why is it caused. metastability - how to fix it FIFO uses ASIC design flow How does synthesis happen Synchronisation vs Asynchronous clock 3rd Interviewer: Equation for power in a resistor Analysis of parallel LC circuit 2 i/p AND gate where each input is getting pwm of period 10. But on input B, an inverter of 1ms delay is attached. What's the resulting waveform? Is it practical to be used with a f/f Transfer characteristic of NOT gate Can NOT gate be used as an amplifier
Sequence detector
1. Frequency divider circuits. 2. JK flip flop truth table and circuit gate based implementation. 3. Sequence detector using FSM for 00100 overlapping. 4. Usage of clock in sequential circuits. 5. setup and hold time. 6. How do you express frequency in terms of setup and hold times. 7. 1 aptitude question. (only this question not answered properly)
Why PMOS is sized larger than NMOS?
Fifo functionality and verilog code to write
explain clock skew
Technical questions: 1. Build a FSM of pattern recognition? 2. What is meta-stability? further more discussion about mean time between failure 3. Diagram of Pull up and pull down transistor network 4. talk about Verilog/HDL experience Also, one of the first question was interviewer wanted to hear in my word my experience and skills mentioned in the CV. So you must be able to explain all your projects and summarize the technical work mentioned in your CV concisely. Soft skills: The HR questions were on company values such as innovation, team work, leadership. For example from your experience, tell us about a time where you showed innovation or leadership, or resolved a issue in a team. I suppose the key here is to show that you will be a good team player and will give credit to the whole team and resolve issues, because from the similarity in the director interview it did feel like they really value team work skills, more than anything.
Q1: Aptitude (trick) questions related to trains
Basic digital design questions such as FSM, STA and verilog
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